Systolic Array Based Convolutional Neural Network Inference on FPGA

Author:

Chua Shi Hui1,Teo T. Hui2,Tiruye Mulat Ayinet1,Wey I-Chyn3

Affiliation:

1. Singapore University of Technology and Design,Engineering Product Development,Singapore

2. Singapore University of Technology and Design,Engineering Product Development, Science Mathematics and Technology,Singapore

3. Artificial Intelligence Research Center, School of Electrical and Computer Engineering College of Engineering, Graduate Institute of Electrical Engineering, Chang Gung University, Chang Gung University,Taiwan

Publisher

IEEE

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Implementation of Physics Informed Neural Networks on Edge Device;2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2023-12-18

2. A Energy-Efficient Re-configurable Multi-mode Convolution Neuron Network Accelerator;2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2023-12-18

3. Systolic Array Architecture for Educational Use;2023 27th International Conference on System Theory, Control and Computing (ICSTCC);2023-10-11

4. A-DSCNN: Depthwise Separable Convolutional Neural Network Inference Chip Design Using an Approximate Multiplier;Chips;2023-07-19

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