A-DSCNN: Depthwise Separable Convolutional Neural Network Inference Chip Design Using an Approximate Multiplier
Author:
Affiliation:
1. Engineering Product Development, Singapore University of Technology and Design, Singapore 487372, Singapore
2. Department of Electrical Engineering, Chang Gung University, Taoyuan City 33302, Taiwan
Abstract
Publisher
MDPI AG
Link
https://www.mdpi.com/2674-0729/2/3/10/pdf
Reference23 articles.
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2. Kulkarni, P., Gupta, P., and Ercegovac, M. (2011, January 2–7). Trading Accuracy for Power with an Underdesigned Multiplier Architecture. Proceedings of the 2011 24th Internatioal Conference on VLSI Design, Chennai, India.
3. Shin, D., and Gupta, S.K. (2010, January 8–12). Approximate logic synthesis for error tolerant applications. Proceedings of the 2010 Design, Automation and Test in Europe Conference and Exhibition (DATE 2010), Dresden, Germany.
4. Low-Power Digital Signal Processing Using Approximate Adders;Gupta;IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.,2013
5. Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications;Mahdiani;IEEE Trans. Circuits Syst. I Regul. Pap.,2010
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