Two-Mask Wafer-Level Vacuum Packaging With Bulk-Si 3D Interconnects for MEMS Devices and Its Package Performances-Reference-Cited by-同舟云学术

Two-Mask Wafer-Level Vacuum Packaging With Bulk-Si 3D Interconnects for MEMS Devices and Its Package Performances

Published:2022-07-15 Issue:14 Volume:22 Page:14522-14530
ISSN:1530-437X
Container-title:IEEE Sensors Journal
language:
Short-container-title:IEEE Sensors J.

Author:

Liang Hengmao¹^ORCID,He Xiao²^ORCID,Xiong Bin³^ORCID

Affiliation:

1. College of Electronic Engineering (College of Artificial Intelligence), South China Agricultural University, Tianhe, China

2. China Electronic Product Reliability and Environmental Testing Research Institute (CEPREI), Guangzhou, China

3. Science and Technology on Microsystem Laboratory, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China

Funder

Basic and Applied Basic Research Foundation of Guangdong Province

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Instrumentation

Link

http://xplorestaging.ieee.org/ielx7/7361/9829891/09799801.pdf?arnumber=9799801

Reference25 articles.

1. Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology

2. Fracture analysis of anodically bonded silicon substrates during the CMP process

3. An All-Silicon Process Platform for Wafer-Level Vacuum Packaged MEMS Devices

4. Wafer level hermetic sealing of MEMS devices with vertical feedthroughs using anodic bonding

5. A Low-Power Oven-Controlled Vacuum Package Technology for High-Performance MEMS

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