Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration-Reference-Cited by-同舟云学术

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

Published:2017-12 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Electron Devices Meeting (IEDM)
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Author:

Mertens H.,Ritzenthaler R.,Pena V.,Santoro G.,Kenis K.,Schulze A.,Litta E. D.,Chew S. A.,Devriendt K.,Chiarella r.,Demuynck S.,Yakimets D.,Jang D.,Spessot A.,Eneman G.,Dangol A.,Lagrain P.,Bender H.,Sun S.,Korolik M.,Kioussis D.,Kim M.,Bu K-.H.,Chen S. C.,Cogorno M.,Devrajan J.,Machillot J.,Yoshida N.,Kim N.,Barla K.,Mocuta D.,Horiguchi N.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8255107/8268301/08268511.pdf?arnumber=8268511

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