Low-temperature atomic-level trimming on Ge interfused surface for gate-all-around Si nanosheets transistors
Author:
Funder
National Natural Science Foundation of China
Strategic Pilot Project of the Chinese Academy of Sciences-Class A
Publisher
Springer Science and Business Media LLC
Link
https://link.springer.com/content/pdf/10.1007/s12598-024-02863-x.pdf
Reference35 articles.
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2. Zhang QZ, Zhang YK, Luo YN, Yin HX. New structure transistors for advanced technology node CMOS ICs. Natl Sci Rev. 2024;11:1. https://doi.org/10.1093/nsr/nwae008.
3. Tian JJ, He YJ, Zhang QZ, Wu CN, Cao L, Yao JX, Mao SJ, Luo YL, Zhang ZH, Li YL, Xu GB, Li B, Han YC, Liu Y, Li JJ, Wu ZH, Wang GL, Kong ZZ, Liu JB, Yang H, Zhang YK, Radamson HH, Yin HX, Luo J, Wang WW. Improving driving current with high-efficiency landing pads technique for reduced parasitic resistance in gate-all-around Si nanosheet devices. ECS J Solid State Sci Tech. 2022;11(3):2162. https://doi.org/10.1149/2162-8777/ac5d64.
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5. Loubet N, Hook T, Montanini P, Yeung CW, Kanakasabapathy S, Guillom M, Yamashita T, Zhang J, Miao X, Wang J, Young A, Chao R, Kang M, Liu Z, Fan S, Hamieh B, Sieg S, Mignot Y, Xu W, Seo SC, Yoo J, Mochizuki S, Sankarapandian M, Kwon O, Carr A, Greene A, Park Y, Frougier J, Galatage R, Bao R, Shearer J, Conti R, Song H, Lee D, Kong D, Xu Y, Arceo A, Bi Z, Xu P, Muthinti R, Li J, Wong R, Brown D, Oldiges P, Robison R, Arnold J, Felix N, Skordas S, Gaudiello J, Standaert T, Jagannathan H, Corliss D, Na MH, Knorr A, Wu T, Gupta D, Lian S, Divakaruni R, Gow T, Labelle C, Lee S, Paruchuri V, Bu H, Khare M. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. In: Proceedings of Symposium on VLSI Technology. Kyoto; 2017. T230. https://doi.org/10.23919/VLSIT.2017.7998183
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