3D Ferroelectric-like NVM/CMOS hybrid chip by sub-400 °C sequential layered integration-Reference-Cited by-同舟云学术

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3D Ferroelectric-like NVM/CMOS hybrid chip by sub-400 °C sequential layered integration

Published:2012-12 Issue: Volume: Page:
ISSN:
Container-title:2012 International Electron Devices Meeting
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Author:

Lien Yu-Chung,Shieh Jia-Min,Huang Wen-Hsien,Hsieh Wei-Shang,Tu Cheng-Hui,Wang Chieh,Shen Chang-Hong,Chou Tung-Huan,Chen Min-Cheng,Huang Jung Y.,Pan Ci-Ling,Lai Yin-Chieh,Hu Chenming,Yang Fu-Liang

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6471855/6478950/06479160.pdf?arnumber=6479160

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Reliability of Multiple-Layer Stacked Gate-All-Around Poly-Si Nanosheet Channel Ferroelectric Hf_xZr_1-xO₂FETs With NH₃ Plasma Treatment;IEEE Transactions on Electron Devices;2023-07

2. Low Thermal Budget Reconfigurable Fully Depleted Silicon on Insulator Field-Effect-Transistors With Embedded Boolean Logic;IEEE Electron Device Letters;2023-02

3. Performance of four-terminal low-temperature polycrystalline-silicon thin-film transistors and their application in CMOS inverters on glass substrates;Japanese Journal of Applied Physics;2018-01-24

4. High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits;Scientific Reports;2017-05-02

5. Monolithic 3D chip integrated with 500ns NVM, 3ps logic circuits and SRAM;2013 IEEE International Electron Devices Meeting;2013-12

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