Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation-Reference-Cited by-同舟云学术

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Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation

Published:2017-12 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Electron Devices Meeting (IEDM)
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Author:

Andrieu F.,Berthelon R.,Boumchedda R.,Tricaud G.,Brunet L.,Batude P.,Mathieu B.,Avelar E.,de Sousa A. Ayres,Cibrario G.,Rozeau O.,Lacord J.,Billoint O.,Fenouillet-Beranger C.,Guissi S.,Fried D.,Morin P.,Noel J. P.,Giraud B.,Thuries S.,Arnaud F.,Vinet M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8255107/8268301/08268428.pdf?arnumber=8268428

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration;IEEE Transactions on Electron Devices;2021-02

2. Novel fine-grain back-bias assist techniques for 3D-monolithic 14 nm FDSOI top-tier SRAMs;Solid-State Electronics;2020-06

3. Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on Chip;ACM Transactions on Design Automation of Electronic Systems;2019-11-14

4. Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-04

5. Physical Mechanisms of Mobility Enhancement in Ultrathin Body GeOI pMOSFETs Fabricated by HEtero-Layer-Lift-Off Technology;IEEE Transactions on Electron Devices;2019-03

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