Novel fine-grain back-bias assist techniques for 3D-monolithic 14 nm FDSOI top-tier SRAMs-Reference-Cited by-同舟云学术

Novel fine-grain back-bias assist techniques for 3D-monolithic 14 nm FDSOI top-tier SRAMs

Published:2020-06 Issue: Volume:168 Page:107720
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Bosch D.,Garros X.,Makosiej A.,Ciampolini L.,Weber O.,Lacord J.,Cluzel J.,Giraud B.,Berthelon R.,Cibrario G.,Brunet L.,Batude P.,Fenouillet-Béranger C.,Lattard D.,Colinge J.P.,Balestra F.,Andrieu F.

Funder

LabEx Minos

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference22 articles.

1. Zimmer B, et al., SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS, In: IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 59, no 12; 2012, p. 853 857.

2. Joshi V, et al. Low-variation SRAM bitcells in 22nm FDSOI technology; 2017, p. T222–T223.

3. O. Thomas et al. Dynamic single-p-well SRAM bitcell characterization with back-bias adjustment for optimized wide-voltage-range SRAM operation in 28nm UTBB FD-SOI, 2014, p. 3.4.1–3.4.4.

4. N. Sugii, Road to Vmin=0.4V LSIs with least-variability FDSOI and back-bias control, IEEE 2011 International SOI Conference, Tempe, AZ, 2011, pp. 1–19.

5. F. Andrieu et al. Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation; 2017, p. 20.3.1–20.3.4.

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