Author:
Ahmed Islam,Nouh Khaled,Abbas Amr
Cited by
5 articles.
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1. System-on-Chip Information Flow Validation Under Asynchronous Resets;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-09
2. Automatic Generation of System Verilog Assertions for Verification of Safety Mechanisms;2024 4th Interdisciplinary Conference on Electrics and Computer (INTCEC);2024-06-11
3. Dual-Edge Triggered Reset Synchronizer for I2C Protocol;Lecture Notes in Electrical Engineering;2024
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