半導体論理開発における検証技術の発展と標準化の動向
Author:
Affiliation:
1. EE Tech Focus, LLC
2. Advanced Computing Project, Computing Laboratory, Fujitsu Ltd.
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
General Earth and Planetary Sciences,General Environmental Science
Link
https://www.jstage.jst.go.jp/article/essfr/16/4/16_272/_pdf
Reference51 articles.
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3. (3) Design Automation Standards Committee, “IEEE Standard for Verilog Hardware Description Language,” IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001), April 2006, doi:10.1109/IEEESTD.2006.99495.
4. (4) J.H. Jiang and S. Devadas, “Logic synthesis in a nutshell,” in Electronic Design Automation, Elsevier, pp.299-404, 2009.
5. (5) Y. Wang and R. Nouta, “System design methodologies-High level synthesis and a VHDL implementation of a practical scheme for UWB communication,” Master's thesis, Delft University of Technology, 2004.
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