Dual-Edge Triggered Reset Synchronizer for I2C Protocol
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-97-2636-3_12
Reference5 articles.
1. Ahmed, Nouh K, Abbas A (2017) Multiple reset domains verification using assertion based verification. In: 2017 IFIP/IEEE International conference on very large scale integration (VLSI-SoC), Abu Dhabi, 2017, pp 1–6
2. Kasim M, Gupta V, Jebin M (2020) Methodology for detection glitch on clock, reset and CDC path. In: Proceedings of the fifth international conference on communication and electronics systems (ICCES 2020) pp 300–304
3. Jones J, Yang S, Greenstreet M (2009) Synchronizer behavior and analysis. In: Proc. IEEE international symposium on circuits and systems (ASYNC 09), IEEE CS Press, 2009, pp 117–126
4. Fawzy M, Elgohary A, Ibrahim H (2020) Noise reduction in reset domain crossings verification using formal versification. IEEE east-west design & test symposium EWDTS 2020, pp 1–5
5. UM10204 I2C-bus specification and user manual Rev. 6–4 April 2014
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