Efficient Configurable Digit-Serial Multiplier Based on Improved Karatsuba Algorithm over GF(2m)
Author:
Affiliation:
1. College of Electronic and Information Engineering Nanjing University of Aeronautics and Astronautics,Nanjing,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10072013/10072295/10072558.pdf?arnumber=10072558
Reference18 articles.
1. Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm
2. Area-Delay Efficient Digit-Serial Multiplier Based on $k$ -Partitioning Scheme Combined With TMVP Block Recombination Approach
3. Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach
4. Area-Delay Efficient Digit-Serial Multiplier Based on -Partitioning Scheme Combined With TMVP Block Recombination Approach;lee;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,0
5. Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b,2)-Way Karatsuba Decomposition
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1. Input–Output Scheduling and Control for Efficient FPGA Realization of Digit-Serial Multiplication Over Generic Binary Extension Fields;Circuits, Systems, and Signal Processing;2024-08-07
2. Digit-Size Selection for FPGA Implementation of Generic Digit-Serial Multiplication Over GF(2m);2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS);2023-09-01
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