Area-Delay Efficient Digit-Serial Multiplier Based on <inline-formula> <tex-math notation="LaTeX">$k$ </tex-math> </inline-formula>-Partitioning Scheme Combined With TMVP Block Recombination Approach-Reference-Cited by-同舟云学术

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Area-Delay Efficient Digit-Serial Multiplier Based on $k$ -Partitioning Scheme Combined With TMVP Block Recombination Approach

Published:2016-07 Issue:7 Volume:24 Page:2413-2425
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Lee Chiou-Yng,Meher Pramod Kumar,Liu Chung-Hsin

Funder

Ministry of Science and Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7498705/07389409.pdf?arnumber=7389409

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Efficient Configurable Digit-Serial Multiplier Based on Improved Karatsuba Algorithm over GF(2m);2022 IEEE 22nd International Conference on Communication Technology (ICCT);2022-11-11

2. Fixed‐latency architecture for multi‐stage algebraic interleavers in interleave division multiple access systems;Electronics Letters;2022-09-21

3. A survey paper on design and implementation of multipliers for digital system applications;Artificial Intelligence Review;2022-01-20

4. Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy;2019 IEEE 37th International Conference on Computer Design (ICCD);2019-11

5. Design of a digit-serial multiplier over GF(2m) using a karatsuba algorithm;Journal of the Chinese Institute of Engineers;2019-08-05

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