Design of a digit-serial multiplier over GF(2m) using a karatsuba algorithm-Reference-Cited by-同舟云学术

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Design of a digit-serial multiplier over GF(2m) using a karatsuba algorithm

Published:2019-08-05 Issue:7 Volume:42 Page:602-612
ISSN:0253-3839
Container-title:Journal of the Chinese Institute of Engineers
language:en
Short-container-title:Journal of the Chinese Institute of Engineers

Author:

Lee Trong-Yen¹,Liu Min-Jea¹,Huang Chia-Han¹,Fan Chia-Chen²,Tsai Chia-Chun³,Wu Haixia⁴

Affiliation:

1. Department of Electrical Engineering, National Taipei University of Technology, Taipei, Taiwan

2. Department of Computer Science, National Chiao Tung University, Hsinchu, Taiwan

3. Department of Computer Science and Information Engineering, Nanhua University, Chiayi, Taiwan

4. School of Information and Electronics, Beijing Institute of Technology, Beijing, China

Publisher

Informa UK Limited

Subject

General Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/02533839.2019.1644200

Reference28 articles.

1. Super Digit-Serial Systolic Multiplier over GF(2^m)

2. Dual basis systolic multipliers for GF(2m)

3. FPGA designs of parallel high performance GF(2/sup 233/) multipliers [cryptographic applications]

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Performance Comparison Review of Multiplier Designs;2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON);2022-12-02

2. A survey paper on design and implementation of multipliers for digital system applications;Artificial Intelligence Review;2022-01-20

3. Area-efficient low-latency polynomial basis finite field GF(2 ) systolic multiplier for a class of trinomials;Microelectronics Journal;2020-03

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