Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/7166375/07166404.pdf?arnumber=7166404
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Area and Delay Trade-Offs in Three-Way Toom-Cook Large Integer Multipliers Implemented on FPGAs;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
2. Efficient Configurable Digit-Serial Multiplier Based on Improved Karatsuba Algorithm over GF(2m);2022 IEEE 22nd International Conference on Communication Technology (ICCT);2022-11-11
3. Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication;Journal of Hardware and Systems Security;2020-01-02
4. Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy;2019 IEEE 37th International Conference on Computer Design (ICCD);2019-11
5. Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-01
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