A Case for Accelerating Software RTL Simulation
Author:
Funder
Army Research Laboratory
Army Research Office
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/40/9130972/09099598.pdf?arnumber=9099598
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. CPGPUSim: A Multi-dimensional Parallel Acceleration Framework for RTL Simulation;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
2. Non-intrusive study on FPGA of the SEU sensitivity on the COTS RISC-V VeeR EH1 soft processor from Western Digital;Microprocessors and Microsystems;2024-03
3. Accelerating RTL Simulation with Hardware-Software Co-Design;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28
4. MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented Model-driven Prototyping;Proceedings of the 34th International Workshop on Rapid System Prototyping;2023-09-21
5. The Case for Performance Interfaces for Hardware Accelerators;Proceedings of the 19th Workshop on Hot Topics in Operating Systems;2023-06-22
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