MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented Model-driven Prototyping-Reference-Cited by-同舟云学术

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MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented Model-driven Prototyping

Published:2023-09-21 Issue: Volume:19 Page:1-7
ISSN:
Container-title:Proceedings of the 34th International Workshop on Rapid System Prototyping
language:
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Author:

Strauch Tobias¹^ORCID

Affiliation:

1. EDAptix, Munich, Germany

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3625223.3649276

Reference17 articles.

1. IEEE "1800-2017 - IEEE Standard for SystemVerilog-Unified Hardware Design Specification and Verification Language". [Online]. Available: https://ieeexplore.ieee.org/document/8299595

2. ISO/IEC "Working Draft Standard for Programming Language C++" Document Number N4835 Date 2019-10-08. [Online]. Available: https://github.com/cplusplus/draft/blob/main/papers/n4835.pdf

3. A. Kölbl, J. Kukula, and R. Damiano, "Symbolic RTL Simulation", Proceeding of the 38th Design Automation Conference, 22-22 June 2001, Las Vegas, NV, USA, pp. 1--6.

4. C. Zivkovic, and C. Grimm, "Symbolic Simulation of SystemC AMS Without Yet Another Compiler", 2018 Forum on Specification & Design Languages, FDL 2018, 10-12 Sep. 2018, Garching, Germany, pp. 1--8.

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