The Case for Performance Interfaces for Hardware Accelerators

Author:

Iyer Rishabh1ORCID,Ma Jiacheng1ORCID,Argyraki Katerina1ORCID,Candea George1ORCID,Ratnasamy Sylvia2ORCID

Affiliation:

1. EPFL, Lausanne, Switzerland

2. UC Berkeley & Google, Berkeley, United States of America

Publisher

ACM

Reference66 articles.

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2. The Economics of ASICs. https://www.electronicdesign.com/technologies/embedded-revolution/article/21808278/ensilica-the-economics-of-asics-at-what-point-does-a-custom-soc-become-viable. Last accessed on 2023-05-16. The Economics of ASICs. https://www.electronicdesign.com/technologies/embedded-revolution/article/21808278/ensilica-the-economics-of-asics-at-what-point-does-a-custom-soc-become-viable. Last accessed on 2023-05-16.

3. Athalye , A. , Kaashoek , M. F. , and Zeldovich , N . Verifying Hardware Security Modules with Information-Preserving Refinement. In Symp. on Operating Sys. Design and Implem. ( 2022 ). Athalye, A., Kaashoek, M. F., and Zeldovich, N. Verifying Hardware Security Modules with Information-Preserving Refinement. In Symp. on Operating Sys. Design and Implem. (2022).

4. AWS Inferentia Accelerators for Deep Learning Inference. https://aws.amazon.com/machine-learning/inferentia/. Last accessed on 2023-05-16. AWS Inferentia Accelerators for Deep Learning Inference. https://aws.amazon.com/machine-learning/inferentia/. Last accessed on 2023-05-16.

5. AWS Nitro System. https://aws.amazon.com/ec2/nitro/. Last accessed on 2023-05-16. AWS Nitro System. https://aws.amazon.com/ec2/nitro/. Last accessed on 2023-05-16.

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1. Achieving Microsecond-Scale Tail Latency Efficiently with Approximate Optimal Scheduling;Proceedings of the 29th Symposium on Operating Systems Principles;2023-10-23

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