An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures

Author:

Singh Adit D.

Publisher

IEEE

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Silent Data Corruption from Timing Marginalities Due to Process Variations;2024 IEEE European Test Symposium (ETS);2024-05-20

2. Scenario-based Test Content Optimization: Scan Test vs. System-Level Test;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22

3. Structural Testing: Vmin Silicon Issues and Solutions;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

4. Automotive Semiconductor Test: Challenges and Solutions towards Zero Defect Quality;2023 45th Annual EOS/ESD Symposium (EOS/ESD);2023-10-02

5. Performance Screening Using Functional Path Ring Oscillators;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-06

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