On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF

Author:

Camacho-Ruiz E.1,Santana-Andreo A.1,Castro-Lopez R.1,Roca E.1,Fernandez F. V.1

Affiliation:

1. IMSE-CNM (CSIC/Universidad de Sevilla),Instituto de Microelectrónica de Sevilla

Publisher

IEEE

Reference17 articles.

1. A novel Physical Unclonable Function using RTN;camacho;Proc of IEEE International Symposium on Circuits and Systems (ISCAS),2022

2. Simulating the impact of random telegraph noise on integrated circuits;saraza-canflanca;Proc International Conference on Synthesis Modeling Analysis and Simulation Methods and Applications to Circuit Design (SMACD),2021

3. A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors

4. Comparison of modeling approaches for transistor degradation: model card adaptations vs subcircuits

5. Statistical Characterization of Time-Dependent Variability Defects Using the Maximum Current Fluctuation

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design considerations for a CMOS 65-nm RTN-based PUF;2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD);2023-07-03

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