Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND-Reference-Cited by-同舟云学术

Comprehensive Design Guidelines of Gate Stack for QLC and Highly Reliable Ferroelectric VNAND

Published:2023-12-09 Issue: Volume: Page:
ISSN:
Container-title:2023 International Electron Devices Meeting (IEDM)
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Author:

Lim Suhwan¹,Kim Taeyoung¹,Myeong Ilho¹,Park Sanghyun¹,Noh Suseong¹,Lee Seung Min¹,Woo Jongho¹,Ko Hanseung¹,Noh Youngji¹,Choi Moonkang¹,Lee Kiheun¹,Han Sangwoo¹,Baek Jongyeon¹,Kim Kijoon¹,Kim Juhyung¹,Jung Dongjin¹,Kim Kwangsoo¹,Yoo Sijung²,Lee Hyun Jae²,Nam Seung-Geol²,Kim Ji-Sung¹,Park Jaewoo¹,Kim Chaeho¹,Kim Seunghyun³,Kim Hyoseok³,Heo Jinseong²,Park Kwangmin¹,Jeon Sanghun⁴,Kim Wanki¹,Ha Daewon¹,Shin Yu Gyun¹,Song Jaihyuk¹

Affiliation:

1. Semiconductor R&D Center, Samsung Electronics Co., Ltd,South Korea

2. Samsung Advanced Institute of Technology

3. Innovation Center, Samsung Electronics Co., Ltd,South Korea

4. KAIST,South Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10413659/10413660/10413820.pdf?arnumber=10413820

Reference8 articles.

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