Understanding the Memory Window of Ferroelectric FET and Demonstration of 4.8-V Memory Window With 20-nm HfO<sub>2</sub>-Reference-Cited by-同舟云学术

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Understanding the Memory Window of Ferroelectric FET and Demonstration of 4.8-V Memory Window With 20-nm HfO₂

Published:2024-08 Issue:8 Volume:71 Page:4655-4663
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Qin Yixin¹^ORCID,Zhao Zijian¹^ORCID,Lim Suhwan²^ORCID,Kim Kijoon²,Kim Kwangsoo²^ORCID,Kim Wanki²,Ha Daewon²^ORCID,Narayanan Vijaykrishnan³^ORCID,Ni Kai¹^ORCID

Affiliation:

1. Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN, USA

2. Samsung Electronics Company Ltd., Hwaseong-si, Gyeonggi-do, Republic of Korea

3. Department of Computer Science and Engineering, Pennsylvania State University, State College, Pennsylvania, PA, USA

Funder

SUPREME and PRISM, two of the Semiconductor Research Corporation (SRC) Joint University Microelectronics Program 2.0 (JUMP 2.0) Centers

NSF

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

https://ieeexplore.ieee.org/ielam/16/10609410/10584070-aam.pdf

Reference36 articles.

1. 3-D NAND Technology Achievements and Future Scaling Perspectives

2. 3D NAND Flash Status and Trends

3. 3D NAND Scaling in the next decade

4. Scaling directions for 2D and 3D NAND cells

5. Architectural and Integration Options for 3D NAND Flash Memories

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