Reliable and Fault Tolerant Systems on Chip Through Design for Testability-Reference-Cited by-同舟云学术

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Reliable and Fault Tolerant Systems on Chip Through Design for Testability

Published:2019-02 Issue: Volume: Page:
ISSN:
Container-title:2019 Amity International Conference on Artificial Intelligence (AICAI)
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Author:

Ahmad Afaq

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8693842/8701225/08701390.pdf?arnumber=8701390

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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3. ASIC vs FPGA based Implementations of Built-In Self-Test;International Journal of Advanced Natural Sciences and Engineering Researches;2023-07-13

4. Integration of Testing Effort Function into Delayed S-Shaped Software Reliability Growth Model with Imperfect Debugging — a Proposed Bokhari Model;Operations Research Forum;2021-10-28

5. The Use of Virtual Reality Applications in Stroke Rehabilitation for Older Adults: Technology Enhanced Relearning;Proceedings of the 6th International Conference on Information and Communication Technologies for Ageing Well and e-Health;2020

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