Author:
Devnath Joydeep Kumar,Surana Neelam,Mekie Joycee
Cited by
5 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel Data;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
2. Process Variation Resilient Current-Domain Analog In Memory Computing;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04
3. Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers;Proceedings of the 28th Asia and South Pacific Design Automation Conference;2023-01-16
4. Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks;2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID);2022-02
5. Fast and Low-Power Quantized Fixed Posit High-Accuracy DNN Implementation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-01