Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers-Reference-Cited by-同舟云学术

Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers

Published:2023-01-16 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 28th Asia and South Pacific Design Automation Conference
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Author:

Glint Tom¹,Prasad Kailash¹,Dagli Jinay¹,Gandhi Krishil¹,Gupta Aryan¹,Patel Vrajesh¹,Shah Neel¹,Mekie Joycee¹

Affiliation:

1. IIT Gandhinagar, India and #SVNIT, India

Funder

Intel Corporation

Semiconductor Research Corporation

MHRD

Science and Engineering Research Board

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3566097.3567866

Reference16 articles.

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2. Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey

3. A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural Networks

4. Xiaochen Guo etal 2010. Resistive computation: Avoiding the power wall with low-leakage STT-MRAM based computing. ACM SIGARCH computer architecture news 38 3 (2010) 371--382. Xiaochen Guo et al. 2010. Resistive computation: Avoiding the power wall with low-leakage STT-MRAM based computing. ACM SIGARCH computer architecture news 38 3 (2010) 371--382.

5. John L Gustafson and Isaac T Yonemoto . 2017. Beating floating point at its own game: Posit arithmetic. Supercomputing frontiers and innovations 4, 2 ( 2017 ), 71--86. John L Gustafson and Isaac T Yonemoto. 2017. Beating floating point at its own game: Posit arithmetic. Supercomputing frontiers and innovations 4, 2 (2017), 71--86.

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