Funder
Ministry of Electronics and Information Technology (MEITY) through the SMDP-C2SD and the Young Faculty Research Fellowship (YFRF) Visvesvaraya Ph.D. Scheme
Science and Engineering Research Board
Semiconductor Research Corporation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
7 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Design of a novel low-latency parameterizable posit adder/subtractor using leading one predictor in FPGA;Digital Signal Processing;2024-12
2. COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN Hardware Accelerators;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06
3. Posit for DNN Architectures;Synthesis Lectures on Engineering, Science, and Technology;2023-09-02
4. FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction;Proceedings of the 50th Annual International Symposium on Computer Architecture;2023-06-17
5. Booth Encoding-Based Energy Efficient Multipliers for Deep Learning Systems;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-06