Author:
Pilato Luca,Saponara Sergio,Fanucci Luca
Cited by
5 articles.
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1. Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination;2023 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE);2023-11-08
2. Full-custom Design of Improved Carry Adder Circuit for CLBs;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
3. An Efficient VLSI Architecture for Analysis of Area, Delay and Power Consumption-A Review;2023 2nd International Conference for Innovation in Technology (INOCON);2023-03-03
4. A Deep Neural Network Accelerator using Residue Arithmetic in a Hybrid Optoelectronic System;ACM Journal on Emerging Technologies in Computing Systems;2022-10-13
5. In-Network Accumulation: Extending the Role of NoC for DNN Acceleration;2022 IEEE 35th International System-on-Chip Conference (SOCC);2022-09-05