Full-custom Design of Improved Carry Adder Circuit for CLBs-Reference-Cited by-同舟云学术

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Full-custom Design of Improved Carry Adder Circuit for CLBs

Published:2023-10-24 Issue: Volume: Page:1-4
ISSN:
Container-title:2023 IEEE 15th International Conference on ASIC (ASICON)
language:
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Author:

Xu Mengfan¹,Zhang Yuejun¹,Zhang Huihong¹,Wen Liang²,Yuan Tengfei¹,Wang Pengjun³,Li Zhiyi¹

Affiliation:

1. Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China,315211

2. China Coast Guard Academy,Department of Electronic Technology,Ningbo,China,315211

3. Wenzhou University,College of Electrical and Electronic Engineering,Wenzhou,China,325035

Funder

National Natural Science Foundation of China

Science and Technology Innovation 2025 Major Project of Ningbo

Natural Science Foundation of Ningbo

Ningbo University

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10395907/10395930/10396489.pdf?arnumber=10396489

Reference13 articles.

1. Optimizing carry-lookahead logic through a comparison of PMOS and NMOS block inversions

2. A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication

3. FPGA Based Performance Comparison of Different Basic Adder Topologies with Parallel Processing Adder

4. Analysis of Low Power 1-bit Adder Cells Using Different XOR-XNOR Gates

5. Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications

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