Author:
Ananthakrishnan ,Ajit Anaswar,Arathi P.V.,Haridas Kiran,Nambiar Niraj Mohan,Devi S.
Cited by
5 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Efficiency Analysis of Adder Architectures: A Comparative Study Across Various Bit Lengths;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28
2. Low Power Microarchitecture Designs of ACS Block in Viterbi Decoder: A Review;Proceedings of the 2023 13th International Conference on Information Communication and Management;2023-11-07
3. Full-custom Design of Improved Carry Adder Circuit for CLBs;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
4. Design of a 4-bit absolute value detector with balanced energy and delay;AIP Conference Proceedings;2023
5. Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA;International Journal of Intelligent Unmanned Systems;2021-02-18