Low Power Microarchitecture Designs of ACS Block in Viterbi Decoder: A Review-Reference-Cited by-同舟云学术

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Low Power Microarchitecture Designs of ACS Block in Viterbi Decoder: A Review

Published:2023-11-07 Issue: Volume: Page:16-20
ISSN:
Container-title:Proceedings of the 2023 13th International Conference on Information Communication and Management
language:
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Author:

Mosbeh Asmaa¹^ORCID,Ibraheem Ali A. Y.¹^ORCID,Mostafa Hassan²^ORCID,Yousef Khalil¹^ORCID

Affiliation:

1. Electrical Engineering Department, Assiut, Egypt, Faculty of Engineering, Assiut University, Egypt

2. Electronics and Communications Department, Cairo, Egypt, Faculty of Engineering, Cairo University,, Egypt

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3640429.3640435

Reference17 articles.

1. Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs

2. Locate: Low-Power Viterbi Decoder Exploration using Approximate Adders

3. A Novel Approach for FPGA Implementation of Register Exchange Based Viterbi Decoder and Re-Encoding based Node Synchronizer

4. Sleepy keeper style based Low Power VLSI Architecture of a Viterbi Decoder applying for the Wireless LAN Operation sustainability

5. Implementation of Radix2 ACS in Adaptive Viterbi decoder

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