1-Transistor 1-Source/Channel/Drain-Diode (1T1D) One-Time-Programmable Memory in 14-nm FinFET-Reference-Cited by-同舟云学术

1-Transistor 1-Source/Channel/Drain-Diode (1T1D) One-Time-Programmable Memory in 14-nm FinFET

Published:2023-03 Issue:3 Volume:44 Page:404-407
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Hsieh E. Ray¹^ORCID,Luo Yu Ming²,Huang Yi Xiang¹,Su Huan Shiang¹,Lin Rui Qi¹,Lin Yu-Hsien¹,Chang Kai Hsiang¹,Shen Ting Ho¹,Liu Chuan Hsi¹

Affiliation:

1. Department of Electrical Engineering, National Central University, Taoyuan, Taiwan

2. Department of Electronics Engineering, National Taiwan Normal University, Taipei City, Taiwan

Funder

National Science and Technology Council (NSTC), Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/55/10053585/10018395.pdf?arnumber=10018395

Reference22 articles.

1. Characterization of Multilayer Metal Gate Fuse in 28-nm CMOS Logic Technology

2. A 16-kb Antifuse One-Time-Programmable Memory in 5-nm High-K Metal-Gate FinFET CMOS Featuring Bootstrap High-Voltage Scheme, Read Endpoint Detection, and Pseudodifferential Sensing

3. The demonstration of low-cost and logic process fully-compatible OTP memory on advanced HKMG CMOS with a newly found dielectric fuse breakdown

4. Electromigration of NiSi poly gated electrical fuse and its resistance behaviors induced by high temperature;kang;Proc IEEE Int Rel Phys Symp,2010

5. A 0.9?m2 1T1R bit cell in 14 nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating;chen;Proc IEEE Symp VLSI Circuits (VLSI-Circuits),2016

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2. A Logic Fully Comparable Single-Supply Capacitor-Less 1-FinFET-1-Source-Channel-Drain-Diode (1T1D) Embedded DRAM MACRO in 16-nm FinFET;IEEE Solid-State Circuits Letters;2023