Efficient high-speed/low-power pipelined architecture for the direct 2-D discrete wavelet transform
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Link
http://xplorestaging.ieee.org/ielx5/82/19472/00899642.pdf?arnumber=899642
Cited by 26 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Memory Efficient Hardware Architecture for 5/3 Lifting-Based 2-D Forward Discrete Wavelet Transform;Microprocessors and Microsystems;2021-11
2. Convolution Based Multilevel DWT Architecture Using Distributed Arithmetic and FIR Bi-orthogonal Filter for Two-Dimensional Data Analysis;Advances in Smart Communication and Imaging Systems;2021
3. Performance Analysis of Booth Multiplier-Based FIR in DWT Image Processing Applications;Springer Proceedings in Materials;2021
4. Novel DWT/IDWT Architecture for 3D with Nine Stage 2D Parallel Processing using Split Distributed Arithmetic;International Journal of Image and Graphics;2020-07
5. Closely-Coupled Lifting Hardware for Efficient DWT Computation in an SoC;Journal of Signal Processing Systems;2019-07-08
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