Automatic configuration generation for FPGA interconnect testing-Reference-Cited by-同舟云学术

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Automatic configuration generation for FPGA interconnect testing

Published: Issue: Volume: Page:
ISSN:
Container-title:Proceedings. 21st VLSI Test Symposium, 2003.
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Author:

Tahoori M.B.,Mitra S.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/8533/26948/01197644.pdf?arnumber=1197644

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. On-Chip Delay Measurement for In-Field Test of FPGAs;2019 IEEE 24th Pacific Rim International Symposium on Dependable Computing (PRDC);2019-12

2. An Integrated Framework for Application Independent Testing of FPGA Interconnect;Journal of Electronic Testing;2019-10

3. On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs;2019 IEEE International Test Conference in Asia (ITC-Asia);2019-09

4. Test Configuration Generation for Different FPGA Architectures for Application Independent Testing;2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID);2019-01

5. A new automatic method for testing interconnect resources in FPGAs based on general routing matrix;IEICE Electronics Express;2015

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