Single Event Latchup (SEL) and Single Event Upset (SEU) Evaluation of Xilinx 7nm Versal™ ACAP programmable logic (PL)
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9679321/9679322/09679343.pdf?arnumber=9679343
Reference16 articles.
1. Neutron, 64 MeV Proton & Alpha Single-event Characterization of Xilinx 16nm FinFET Zynq® UltraScale+™ MPSoC
2. Single-Event Latch-Up: Increased Sensitivity From Planar to FinFET
3. Single-Event Evaluation of Xilinx 16nm UltraScale+™ Single Event Mitigation IP
4. Test Methodology & Neutron Characterization of Xilinx 16nm Zynq® UltraScale+™ Multi-Processor System-on-Chip (MPSoC)
5. Neutron, 64 MeV Proton, Thermal Neutron and Alpha Single-Event Upset Characterization of Xilinx 20nm UltraScale Kintex FPGA
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