Single-Event Evaluation of Xilinx 16nm UltraScale+™ Single Event Mitigation IP
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8581398/8584255/08584298.pdf?arnumber=8584298
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Investigation of the Xilinx SEM Core on a Zynq-Based Software-Defined Radio Under Proton Irradiation;2023 IEEE Radiation Effects Data Workshop (REDW) (in conjunction with 2023 NSREC);2023-07
2. AnoDe: A Log-based Self-Supervised Framework to Detect Scrubber Failures in SRAM-FPGA;2022 IEEE 27th Pacific Rim International Symposium on Dependable Computing (PRDC);2022-11
3. Analysis of the impact on soft error in AXI CDMA based on Xilinx Zynq-7000 FPGA;Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment;2022-08
4. Single Event Latchup (SEL) and Single Event Upset (SEU) Evaluation of Xilinx 7nm Versal™ ACAP programmable logic (PL);2021 IEEE Nuclear and Space Radiation Effects Conference (NSREC);2021-07
5. Reliability assessment on 16 nm ultrascale+ MPSoC using fault injection and fault tree analysis;Microelectronics Reliability;2021-05
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