28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET-Reference-Cited by-同舟云学术

28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET

Published:2017-02 Issue: Volume: Page:
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Container-title:2017 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Kull Lukas,Luu Danny,Menolfi Christian,Braendli Matthias,Francese Pier Andrea,Morf Thomas,Kossel Marcel,Yueksel Hazar,Cevrero Alessandro,Ozkaya Ilter,Toifl Thomas

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7866667/7870233/07870467.pdf?arnumber=7870467

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