Author:
Pillai R.V.K.,Shah S.Y.A.,Al-Khalili A.J.,Al-Khalili D.
Cited by
5 articles.
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1. A Deeply Pipelined FMA Unit for High Performance RISC-V Processor;2023 2nd International Conference on Computing, Communication, Perception and Quantum Technology (CCPQT);2023-08-04
2. Self-timed Fused Multiplier-Adder Pipeline Optimization;2023 International Russian Smart Industry Conference (SmartIndustryCon);2023-03-27
3. Energy Efficient Speed-Independent 64-bit Fused Multiply-Add Unit*;2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus);2019-01
4. Implementation of Low Power and Area Efficient Floating-Point Fused Multiply-Add Unit;Proceedings of the International Conference on Soft Computing Systems;2015-12-29
5. Low‐precision DSP‐based floating‐point multiply‐add fused for Field Programmable Gate Arrays;IET Computers & Digital Techniques;2014-07