A Deeply Pipelined FMA Unit for High Performance RISC-V Processor-Reference-Cited by-同舟云学术

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A Deeply Pipelined FMA Unit for High Performance RISC-V Processor

Published:2023-08-04 Issue: Volume: Page:
ISSN:
Container-title:2023 2nd International Conference on Computing, Communication, Perception and Quantum Technology (CCPQT)
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Author:

Qi Yu¹,Chen Mengxue¹,Li Guilan¹,Li Gaosheng¹,He Meisheng²,Xu Bangjian³

Affiliation:

1. Hunan University,College of Electrical and Information Engineering,Changsha,China

2. Hunan Institute of Traffic Engineering,School of Transportation Engineering,Hengyang,China

3. Hunan University,College of Computer Science and Electronic Engineering,Changsha,China

Funder

Natural Science Foundation of Hunan Province

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10336570/10336571/10336576.pdf?arnumber=10336576

Reference19 articles.

1. Design of a new floating point multiplier based on hybrid compression structure;Yao;Microelectronics and Computer,2021

2. Design and analysis of inexact floating-point multiplier;Yin;Application of Electronic Technology,2016

3. Design of the IBM RISC System/6000 floating-point execution unit

4. Itanium processor microarchitecture

5. NVIDIA’s Fermi: The First Complete GPU Computing Architecture, Nvidia Fermi White paper;Glaskowsky

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