Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits-Reference-Cited by-同舟云学术

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Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits

Published:2002-05 Issue:5 Volume:21 Page:544-553
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Orshansky M.,Milor L.,Pinhong Chen ,Keutzer K.,Chenming Hu

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/21547/00998626.pdf?arnumber=998626

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