Design of SRAM Cell Using FinFET for Low Power Applications
Author:
Affiliation:
1. Vignana Bharathi Institute of Technology Ghatkesar,Department of Electronics and Communication Engineering,Hyderabad,Telangana
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10560478/10560483/10561144.pdf?arnumber=10561144
Reference14 articles.
1. Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications
2. Design of Polymer-Based Trigate Nanoscale FinFET for the Implementation of Two-Stage Operational Amplifier
3. An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs
4. Effect of processor performance variability in negative capacitance FET technology;Amrouch;IEEE, Exchanges regarding Circuits and Systems
5. Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology
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