1. Automatic Test Pattern Generation;Electronic Design Automation for IC System Design, Verification, and Testing;2016-04-14
2. Path Delay Test Generation Toward Activation of Worst Case Coupling Effects;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2011-11
3. Multiple Coupling Effects Oriented Path Delay Test Generation;26th IEEE VLSI Test Symposium (vts 2008);2008-04
4. Static Crosstalk Noise Analysis with Transition Map;4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008);2008-01