A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment-Reference-Cited by-同舟云学术

A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment

Published:2021-11-22 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)
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Author:

Lee Tzung-Je¹,Su Wen-Jian¹,Tolentino Lean Karlo S.¹,Wang Chua-Chin¹

Affiliation:

1. National Sun Yat-Sen University,Department of Electrical Engineering,Kaohsiung,Taiwan,80424

Funder

Ministry of Science and Technology (MOST), Taiwan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9687621/9687623/09687736.pdf?arnumber=9687736

Reference11 articles.

1. Design of $2 \times {\rm V}_{\rm DD}$-Tolerant I/O Buffer With PVT Compensation Realized by Only $1 \times {\rm V}_{\rm DD}$ Thin-Oxide Devices

2. Computation of switching noise in printed circuit boards

3. A method of leakage reduction and slew-rate adjustment in 2xVDD output buffer for 28 nm CMOS technology and above;tsai;Proc 2016 International Conference on IC Design and Technology (ICICDT),2016

4. A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique

5. Power sequence free 400Mbps 90µW 6000µm² 1.8V–3.3V stress tolerant I/O buffer in 28nm CMOS

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5. A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19