A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique

Author:

Lee Tzung-JeORCID,Huang Ssu-Wei,Wang Chua-ChinORCID

Funder

Ministry of Science and Technology, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. 2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues;Integration;2024-09

2. A 3.2-GHz 0.3/0.5 V 16-nm FinFET I/O Buffer With Low-Power PVT Compensation Circuit;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology;IEEE Journal of Solid-State Circuits;2024

4. A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

5. A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19

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