The influence of shallow trench isolation angle on hot carrier effect of STI-based LDMOS transistors
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8062165/8069099/08069149.pdf?arnumber=8069149
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Substrate Current Improvement and Investigation in Low Voltage Power Ldmos with A Novel Design;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17
2. A Study of Ldmos With High Breakdown Voltage and Low On-Resistance in 22Nm Technology;2022 China Semiconductor Technology International Conference (CSTIC);2022-06-20
3. Investigation and Demonstration of Hot Carrier Effect in LDMOS Transistors with Ultra-Shallow Trench Isolation;2020 China Semiconductor Technology International Conference (CSTIC);2020-06-26
4. Demonstration of improvement of specific on-resistance versus breakdown voltage tradeoff for low-voltage power LDMOS;Microelectronics Journal;2019-06
5. Hot-Carrier Degradation in Power LDMOS: Selective LOCOS- Versus STI-Based Architecture;IEEE Journal of the Electron Devices Society;2018
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