1. Best-in-class LDMOS with ultra-shallow trench isolation and p-buried layer from 18V to 40V in 0.18μm BCD technology;Jin,2017
2. A novel divided STI-based nLDMOSFET for suppressing HCI degradation under high gate bias stress;Mori,2018
3. Planar dual gate oxide LDMOS structures in 180nm power management technology;Sharma,2012
4. Low on-resistance high voltage thin layer SOI LDMOS transistors with stepped field plates;Hara,2017
5. The influence of shallow trench isolation angle on hot carrier effect of STI-based LDMOS transistors;Alimin,2017