A Study of Ldmos With High Breakdown Voltage and Low On-Resistance in 22Nm Technology
Author:
Affiliation:
1. Semiconductor Manufacturing International Corporation (SMIC),Beijing,China,100176
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9856647/9856709/09856900.pdf?arnumber=9856900
Reference11 articles.
1. Channel Length Scaling Limit for LDMOS Field-Effect Transistors: Semi-classical and Quantum Analysis
2. Novel LDMOS Optimizing Lateral and Vertical Electric Field to Improve Breakdown Voltage by Multi-Ring Technology
3. A study of 28nm LDMOS HCI improvement by layout optimization
4. Evaluation of Hot-Electron Effect on LDMOS Device and Circuit Performances
5. The influence of shallow trench isolation angle on hot carrier effect of STI-based LDMOS transistors
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