Design of low power two bit magnitude comparator using adiabatic logic
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/7818101/7824673/07824703.pdf?arnumber=7824703
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Study of Adiabatic Logic-Based Combinational and Sequential Circuits for Low-Power Applications;Low Power Architectures for IoT Applications;2023
2. Design of Adiabatic Logic Two Tail Comparator for Low Power and Analyze with CMOS Comparator;2022 4th International Conference on Advances in Computing, Communication Control and Networking (ICAC3N);2022-12-16
3. A High-speed Low-power CMOS-Memristor Based Hybrid Comparator Using m_GDI Technique for IoT Applications;2022 IEEE International Symposium on Smart Electronic Systems (iSES);2022-12
4. Performance Analysis of Low Powered Battery Management Circuit Using Adiabatic Logic;2022 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2022-02-19
5. Evaluation and Performance Analysis of Magnitude Comparator for High-Speed VLSI Applications;Intelligent Systems and Sustainable Computing;2022
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