Dual standard re-configurable hardware interleaver for turbo decoding
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4549864/4556149/04556314.pdf?arnumber=4556314
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Energy Aware Mapping for Reconfigurable Wireless MPSoCs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-02
2. A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis;IEEE Journal of Solid-State Circuits;2013-11
3. System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor;International Journal of Embedded and Real-Time Communication Systems;2010-07
4. Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding;Journal of Signal Processing Systems;2009-07-17
5. System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor;Innovations in Embedded and Real-Time Systems Engineering for Communication
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