Design and Implementation of a 3.9-to-5.3 GHz 65 nm Cryo-CMOS LNA with an Average Noise Temperature of 10.2K
Author:
Affiliation:
1. University of Massachusetts,Department of Electrical and Computer Engineering,Amherst,USA
Funder
DARPA
ONR
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9865233/9865240/09865392.pdf?arnumber=9865392
Reference11 articles.
1. 13.1 A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology
2. 13.2 A Fully-Integrated 40-nm 5-6.5 GHz Cryo-CMOS System-on-Chip with I/Q Receiver and Frequency Synthesizer for Scalable Multiplexed Readout of Quantum Dots
3. Characterization of Shot Noise Suppression in Nanometer MOSFETs
4. A Cryogenic Broadband Sub-1-dB NF CMOS Low Noise Amplifier for Quantum Applications
5. A Noise-Temperature Measurement System Using a Cryogenic Attenuator;fernandez;JPL TMO Progress Report,1998
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2. A 4-to-6-GHz Cryogenic CMOS LNA With 4.4-K Average Noise Temperature in 22-nm FDSOI;IEEE Microwave and Wireless Technology Letters;2024-04
3. 29.3 A Cryo-CMOS Receiver with 15K Noise Temperature Achieving 9.8dB SNR in 10μs Integration Time for Spin Qubit Readout;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
4. Cryo-CMOS Dual-Qubit Homodyne Reflectometer Array With Degenerate Parametric Amplification;IEEE Journal of Solid-State Circuits;2024
5. A Cryogenic Four-Channel C-Band Low-Noise Amplifier MMIC in 50-nm Metamorphic High-Electron-Mobility-Transistor Technology;2023 IEEE/MTT-S International Microwave Symposium - IMS 2023;2023-06-11
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