PROSA: Protocol-Driven Network on Chip Architecture

Author:

Alonso Miguel GorguesORCID,Flich Jose

Funder

Spanish Ministerio de Economía y Competitividad (MINECO)

FEDER funds

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Signal Processing

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Dual Diagonal Mesh: An Optimal Memory Cube Network Under Geometric Constraints;2023 Eleventh International Symposium on Computing and Networking (CANDAR);2023-11-28

2. A traffic-aware memory-cube network using bypassing;Microprocessors and Microsystems;2022-04

3. Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-Chip;2021 58th ACM/IEEE Design Automation Conference (DAC);2021-12-05

4. Automated synthesis of custom networks-on-chip for real world applications;Proceedings of the 39th International Conference on Computer-Aided Design;2020-11-02

5. A Survey on Network on Chip Routing Algorithms Criteria;Advances on Smart and Soft Computing;2020-10-20

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